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Analog Circuit Design

Op-amp gain, closed-loop bandwidth, slew rate, comparator hysteresis and difference/instrumentation amplifiers, plus reference tables for common parts and configurations.

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Gain, bandwidth, slew and hysteresis figures use an ideal single-pole model. Real amplifiers add open-loop roll-off, offset, noise and stability limits — always verify against the op-amp datasheet and simulate your circuit.

Op-Amp Gain (Inverting / Non-Inverting)

Inverting: A = −Rf/Rin. Non-inverting: A = 1 + Rf/Rin. Enter a signal Vin to read the output levels.
V
Ω
Ω
Inverting gain (−Rf/Rin)
Inverting Vout = A·Vin
Non-inverting gain (1+Rf/Rin)
Non-inverting Vout = A·Vin
Real swing is limited by the supply rails and the output stage — the ideal multiply only holds within the linear output range.

Closed-Loop Bandwidth (Gain–Bandwidth Product)

Single-pole closed-loop −3 dB bandwidth = GBW ÷ Acl.
V/V
Hz
Closed-loop −3 dB bandwidth
Raising the gain proportionally lowers the bandwidth: Acl × BW is a constant for a given amplifier.

Slew Rate & Full-Power Bandwidth

Full-power bandwidth fmax = SR ÷ (2π·Vp); minimum slew for a sine = 2π·f·Vp.
V/µs
V
Hz
Full-power bandwidth fmax
Min slew rate at f
If the required SR exceeds the part spec, the output distorts (triangular limiting) even before the −3 dB bandwidth is reached.

Comparator Hysteresis (Non-Inverting)

With feedback R1 (output to + input) and R2 (+ input to Vref): VT+ = (Voh·R2 + Vref·R1)/(R1+R2), VT− = (Vol·R2 + Vref·R1)/(R1+R2).
Ω
Ω
V
V
V
Upper threshold VT+
Lower threshold VT−
Hysteresis width
Hysteresis widens with (Voh−Vol)·R2/(R1+R2). Open-drain comparators need a pull-up that sets Voh.

Instrumentation Amplifier Gain (3-Op-Amp)

A = 1 + 2·R1/Rg. A single external Rg sets the gain; the diff stage is usually resistor-trimmed to unity.
Ω
Ω
Instrumentation gain
The input pair only handles the differential signal, giving high common-mode rejection — ideal for bridge and sensor front ends.

Difference Amplifier (Subtractor)

Vout = (Rf/Rin)·(V2 − V1). Resistor ratio matching sets common-mode rejection.
Ω
Ω
V
V
Vout = (Rf/Rin)(V2−V1)
Use tightly matched resistor pairs (0.1 % or a single packaged network) to keep CMRR high.

Op-Amp Noise Analysis (Non-Inverting)

Total RTI noise = √(En² + 4kT·(Rs + Rf∥Rin) + In²·(Rs² + (Rf∥Rin)²)); output noise = RTI × (1+Rf/Rin) × √BW.
nV/√Hz
pA/√Hz
Ω
Ω
Ω
Hz
Noise gain 1+Rf/Rin
Resistor thermal noise
Voltage-noise contribution
Current-noise contribution
Total input-referred (RTI) noise
Total output (RTO) noise
Noise values are RTI/RTO RMS estimates. 4kT at ~300 K is 4.14×10⁻²¹ J; the bias/offset current here adds noise mainly through the source and feedback impedances. Real parts list noise at 1 kHz and rise at low frequency (flicker 1/f) — include the 1/f corner in BW estimates.

Op-Amp DC Offset & Error Budget

Worst-case output offset = (Vos + Ib·|ReQ−Rs| + Io·ReQ) × (1+Rf/Rin); gain error ≈ ±2·tol from the resistor ratio pair.
µV
nA
nA
Ω
Ω
%
Voltage gain 1+Rf/Rin
Offset from Vos (out)
Bias-current mismatch (out)
Offset-current effect (out)
Gain error from tolerance
Total worst-case output offset
Match the two input impedances (make ReQ = Rs) to cancel bias-current offset; only the offset current Io then remains. Resistor tolerance sets the gain accuracy — a 1% pair gives ~±2% worst-case gain error.

📊 Schematic Diagrams

Simplified standard configurations showing input, feedback network and output path.

INVERTING AMPLIFIER · A = \u2212Rf/Rin Vin + Rin + GND Rf Vout i (Rin)

Inverting amplifierVin drives Rin into the summing node; Rf from output back to the node holds it near the + input (virtual ground), producing Vout = −(Rf/Rin)·Vin with inverted polarity.

NON-INVERTING AMPLIFIER · A = 1 + Rf/Rin Vin + + Rin GND Rf Vout signal into + input (high Zin)

Non-inverting amplifierVin feeds the + input directly (very high input impedance); the Rf/Rin divider sets the gain 1 + Rf/Rin with the same polarity as the input.

COMPARATOR WITH HYSTERESIS Vin + + Vout R1 fb R2 Vref + input node

Comparator with hysteresisR1 feeds a little of the output back into the + node, while R2 pulls it to Vref. That feedback splits the trip point into VT+ and VT− and rejects noise at the threshold.

INSTRUMENTATION AMPLIFIER · A = 1 + 2R1/Rg Vin+ R1 Rg shared Rg Vin− Vout difference stage (typically unity)

3-op-amp instrumentation amplifierTwo input amplifiers each add R1 with a common Rg between them giving gain 1 + 2R1/Rg, while a difference stage cancels the common-mode levels of the two inputs.

DIFFERENCE AMPLIFIER · Vout = (Rf/Rin)(V2−V1) V1 Rin + V2 R2 R1 Rf Vout with R1=Rf, R2=Rin the gain is A = Rf/Rin

Difference amplifier (subtractor)V1 drives the − input through Rin while V2 reaches the + input scaled by R2; with R1=Rf and R2=Rin the output becomes (Rf/Rin)(V2 − V1), subtracting common-mode voltages.

UNITY-GAIN BUFFER (FOLLOWER) · A = 1 Vin + Vout Vout = Vin high Zin, low Zout

Unity-gain bufferThe output is wired straight back to the − input, forcing Vout to track Vin exactly (A = 1) with near-infinite input impedance to isolate the source from the load.

GAIN vs FREQUENCY · GBP = Acl × BW dB f → open loop (−20 dB/dec) closed loop at Acl GBW −3 dB

Open-loop vs closed-loop responseOpen-loop gain rolls off at −20 dB/decade and reaches unity at the gain–bandwidth product GBW. A closed-loop gain Acl holds its flat value only until f = GBW / Acl, where the response starts rolling off.

SLEW-RATE LIMITING · SR = dv/dt ideal sine slew-limited SR

Slew-rate limiting waveformIf the required slope 2πf·Vp exceeds the op-amp slew rate, the output cannot follow the sine and its edges flatten into straight, limited slopes — a triangular limit that distorts before the −3 dB bandwidth is reached.

NOISE SOURCES · RTI ≈ √(En² + 4kTR + In²R²) Rs V-source En en (V/√Hz) in + Rf Rin Vout thermal 4kTR √BW & Acl raise output noise

Op-amp noise sourcesThe amplifier has a series voltage-noise source En at the + input and current-noise sources In at each input. Source and feedback resistors add thermal noise 4kTR. Each density is multiplied by √BW and the noise gain to get output RMS noise.

OFFSET & BIAS SOURCES · Vout = (Vos + ΔI·R)·Acl + Vos + Rf Rin Ib− Ib+ Vout ΔI = Ib mismatch match Rs = Rf‖Rin to null Ib·ΔR

Offset & bias sourcesAn input-referred offset voltage Vos and bias currents Ib leaving each input are the DC error sources. The output offset equals the input errors times the noise/DC gain; matching the two input impedances cancels the bias-current term.

OP-AMP · CAPACITIVE LOAD V+ V− out Riso Cload gate C load + Riso form a pole → isolate, keep loop stable Ri small; C creates extra pole in loop gain

Driving a capacitive loadA large capacitance at the op-amp output introduces a pole inside the feedback loop that erodes phase margin and can cause ringing or oscillation. Inserting a small series resistor Ri isolates the capacitor from the loop.

📚 Analog Reference Tables

Condensed specs for common configurations, op-amps, voltage references and comparators. Values are typical — check the datasheet for your exact part.

Op-Amp Configurations at a Glance

ConfigurationTransferNotes
InvertingA = −Rf/RinInput to virtual ground; negative polarity
Non-invertingA = 1 + Rf/RinVery high input impedance
Unity followerA = 1Buffer: max Zin, low Zout
Difference (subtractor)Vout = (Rf/Rin)(V2−V1)Rejects common-mode
IntegratorVout = −(1/RC)∫Vin·dtActive LP / ramp; needs reset bleed
Transimpedance (I→V)Vout = −Rf·IinPhotodiode / sensor front end

Common Op-Amp Families

PartTypeSupplyGBWSRNotes
LM358 / LM324dual / quad3–32 V1 MHz0.3 V/µsCheap single-supply, rail inputs
LM741single±5–±18 V1.5 MHz0.5 V/µsClassic BJT; no rail-to-rail
TL071 / 72 / 74JFET±5–±18 V3 MHz13 V/µsLow input bias current
NE5532dual±3–±18 V10 MHz9 V/µsLow noise; low-Z sources
OPA2333zero-drift1.8–5.5 V350 kHz0.16 V/µsVery low offset / drift
MCP6001CMOS1.8–6 V1 MHz0.6 V/µsSingle-supply rail-to-rail
OPA347micro2.3–5.5 V350 kHz0.17 V/µsLow power, battery apps

Voltage Reference Options

OptionTypical accuracyTempco / driftNotes
LM4040±0.1–2 %20–100 ppm/°CLow-cost 2.5 / 4.096 V shunt
TL431±0.5–1 %30–50 ppm/°CProgrammable 2.5–36 V, very cheap
REF5025±0.05 %3 ppm/°CLow-noise 2.5 V precision series
REF03±0.6 %50 ppm/°C2.5 V buffered
REF34xx±0.05 %6 ppm/°CNanopower rail-to-rail
MCU internalpoor–fairlargeCoarse rails / trimming only
Zener±5 %highAvoid for precision

Common Comparators

PartPropagationOutputNotes
LM393 / LM339~1.3 µsopen–collectorNeeds pull-up; add hysteresis
LM311200 nsopen–collectorFast, TTL output, optional strobe
TLV35014.5 nspush–pullHigh-speed single-supply
ADCMP6008 nsLVTTLFast CMOS, quiescent friendly
MAX9028push–pullNanopower, low hysteresis
Op-amp as compslowBeware phase-inversion; output saturates