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Power Design

Switch-mode and linear power design: buck/boost duty and ripple, heatsink selection, LDO dissipation and output filter cutoff.

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Duty ratios, ripple and thermal figures are engineering estimates. Always verify against the converter's datasheet, thermal model and derating curves.

Buck Converter (Step-Down)

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Ideal CCM duty D = Vout ÷ Vin; inductor ripple ΔI = (Vin − Vout) × D / (f × L).

Input Vin

Output Vout

Switching frequency f

Inductance L

Max load Iout

Duty D

—

Inductor ripple ΔI

—

CCM min load (ΔI/2)

—

Idealized CCM. Below ΔI/2 the converter enters DCM; real duty is raised by switch/diode drops and load.

Boost Converter (Step-Up)

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Ideal CCM duty D = 1 − Vin ÷ Vout; switch stress ≈ Vout.

Input Vin

Output Vout

Duty D

—

Switch stress

—

Idealized; real topologies add rectifier & switch drops (≈0.5–1 V) and practical duty is limited (often < 0.9).

Heatsink & Junction Temperature

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Tj = Ta + Pd × (Rθjc + Rθcs + Rθsa).

Ambient Ta

°C

Power Pd

Rθ j-c

°C/W

Rθ c-s

°C/W

Rθ s-a

°C/W

Max allowed Tj

°C

Junction temp Tj

—

Thermal margin

—

Separate the resistor chain to solve the heatsink Rθs-a you need for a target Tj. Keep margin from the max-junction rating.

Linear Regulator Power & Efficiency

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Pd = (Vin − Vout) × Iout; η ≈ Vout ÷ Vin.

Input Vin

Output Vout

Load current Iout

Dropout (Vin − Vout)

—

Dissipated Pd

—

Efficiency η

—

All of (Vin−Vout)·Iout becomes heat. A low input voltage or a switching regulator avoids large losses in linear pass devices.

LC Output Filter Cutoff

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fc = 1 ÷ (2π√(L·C)).

Inductance L

Capacitance C

Cutoff fc

—

Set fc well above the ripple you want less of and below any frequency you must pass. Add ESR for damping.

Bulk Capacitor Hold-Up

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t = C × (Vs² − Ve²) ÷ (2P); required C = 2Pt ÷ (Vs² − Ve²). Bulk capacitance keeps a rail alive for a short time after input dropout, using the energy stored in Vs² − Ve².

Capacitance C

Start voltage Vs

Minimum Ve

Load power P

Hold-up time

—

Target hold-up

Required C

—

Ve is the minimum input voltage the downstream converter can still regulate from. Only the energy between Vs and Ve is usable; set a target hold-up and read off the capacitance you need.

Feedback Divider / Output Set

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Vout = Vref × (1 + R1 ÷ R2); R1 = R2 × (Vout/Vref − 1). Regulators regulate so the feedback pin sits at Vref, so the divider ratio sets the output voltage.

Reference Vref

Upper R1

Lower R2

Target Vout

Output Vout

—

R1 needed for target

—

Keep the divider current well above the feedback pin's input-bias current (R2 in the kΩ–MΩ range). A feed-forward cap in parallel with R1 sharpens loop response.

Power MOSFET Switching & Gate Loss

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Psw = ½ × Vin × I × fsw × (tr + tf); Pgate = Vg × Qg × fsw. Total = conduction + switching + gate losses.

Off-state voltage Vin

Drain current I

Switching freq fsw

Rise time tr

Fall time tf

Total gate charge Qg

Drive voltage Vg

Rds(on) at Tj

Switching loss

—

Gate loss

—

Conduction Pd

—

Total loss

—

Switching loss scales with fsw and with the V·I overlap time (tr+tf). Fast gate drive (low Rg, high I) shortens tr/tf but raises drive ringing and EMI. Conduction loss is Rds(on)·I²·D.

SEPIC / Ćuk Duty & Voltage Stress

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Ideal CCM duty D = Vout ÷ (Vin + Vout); switch/coupling-cap voltage stress ≈ Vin + Vout. Non-inverting output from a variable input (Vin can be above or below Vout).

Input Vin

Output Vout

Duty D

—

Switch / cap stress

—

Coup. cap avg V

—

Both stages share one demagnetizing path per phase; the coupling capacitor must be a low-ESR film or ceramic sized for the AC ripple current. Duty → 1/2 at Vin = Vout.

Ćuk (Inverting) Duty & Clamp Stress

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Input Vin

Output |Vout|

Ideal duty D

—

Switch / cap stress

—

Coup. cap avg V

—

The output is inverted relative to the input — confirm your design accepts a negative rail. The coupling capacitor (a film or low-ESR type) transfers charge between the two inductors and carries large AC current; size it for ripple and voltage stress ≈ Vin + |Vout|. D → 1/2 when Vin = |Vout|.

Buck Output Ripple & Cap Sizing

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Capacitance term ΔVc = ΔI ÷ (8·C·fsw); ESR term ΔVesr = ΔI·ESR. Total ripple ≈ ΔVc + ΔVesr (ESR usually dominates on low-C high-f designs).

Inductor ripple ΔI

Switching freq fsw

Output cap C

Cap ESR

ΔVc (capacitance)

—

ΔVesr (ESR)

—

Total ripple ΔV

—

Ripple estimates assume a triangular inductor current. When ESR dominates (most electrolytic/aluminum caps), ripple is roughly-independent of C; adding parallel low-ESR ceramics shrinks the ESL/ESR spike at the network's resonant frequency. Estimates only — check the part's ripple-current rating and effective capacitance at the DC bias.

RC Snubber (Damping)

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Damp the V·I ringing: energy Es = ½·L·I². Choose C ≥ L·I² ÷ V², then R = √(L/C). Snubber loss ≈ ½·C·V²·fsw — a small C is key to keeping loss low.

Parasitic L (net)

Peak current I

Node voltage V

Switching freq fsw

Min cap C

—

Damper R

—

Snubber loss

—

L is the total stray inductance of the switching loop you cannot reduce inline. Shrinking the R·C time constant below the ringing period critically-damps it; too large a C wastes power and slows the edge. Tune with a scope — pick R for the lowest overshoot, then confirm the added loss is acceptable.

Buck Inductor & CCM Boundary

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For a buck, L sets the current ripple ΔI = r·Iout. Pick L so the ripple fraction r is sensible, then check the CCM boundary Lccm = (Vin−Vout)·D/(2·fsw·Iout), D = Vout/Vin.

Input Vin

Output Vout

Output current Iout

Switching freq fsw

Ripple ratio r

—

Duty D

—

Peak ripple ΔI

—

Inductance L

—

CCM boundary L

—

Smaller L allows faster transient response but rises ripple, output voltage ripple and peak inductor current; bigger L reduces ripple but slows the loop. Keep r roughly 0.2–0.4 and stay above Lccm for CCM — operating in DCM changes the response and losses.

Flyback Duty & Switch Stress

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For CCM flyback, D = Vout/(Vout + Vin·(Np/Ns)). The primary switch sees Vin plus the reflected output Vout·(Np/Ns) while off, driving clamp and snubber needs.

Input Vin

Output Vout

Turns ratio Np/Ns

—

Duty D

—

Reflected Vout

—

Switch stress

—

The leakage inductance causes a high spike on top of the reflected voltage — allow margin and add an RCD clamp or snubber. Lower Np/Ns reduces primary stress but raises the secondary diode reverse voltage (Vout + Vin·Ns/Np).

Input Inrush Current

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Charging input capacitance through its ESR/line resistance: peak I = Vin/R, settling τ = R·C, stored energy ½·C·Vin².

Input Vin

Input capacitance C

µF

Series R (ESR+line)

Peak inrush

—

Charge time τ

—

Stored energy E

—

Peak inrush can far exceed the steady-state rating of the bulk capacitor. Limit it with a soft-start (NTC, resistor plus relay, or a current-limited pre-charge) and check the source (fuse, bridge diode) for the pulse. τ ≈ 5·R·C for full charge.

⛓️ SMPS Topologies at a Glance

Ideal CCM relations. Real duty needs adjustment for switch and diode losses.

Topology	Ideal Vout	Switch stress	Notes
Buck	≈ D·Vin	< Vin	1 inductor, simple, most common
Boost	≈ Vin/(1−D)	≈ Vout	1 inductor, wide input, ratio limited
Buck-Boost	−D·Vin/(1−D)	Vin+\|Vout\|	Inverting, 1 inductor
SEPIC / Cuk	usually ±	≈ Vin+Vout	2 inductors or coupled L, non-inverting

🔋 Common Power Rails

Rail	Typical use
1.2 V	Core / low-voltage logic — watch load transients
1.8 V	DDR, I/O, 1.8 V MCU domains
2.5 V	FPGA I/O / legacy logic
3.3 V	Logic, MCU, most mixed-signal I/O
5 V	USB VBUS, logic, older peripherals
12 V	Fans, motors, 12 V bus

🌡️ Typical Thermal Resistance by Package

Package	Typical Rθ j-a
SOT-23	200–350 °C/W
SOT-223	120–170 °C/W
SOIC-8	150–170 °C/W
DPAK (TO-252)	60–100 °C/W
D2PAK (TO-263)	40–60 °C/W
TO-220	50–70 °C/W

🔌 Decoupling / Bypass Guidelines

Frequency / domain	Suggested capacitor
Bulk / sub-1 kHz (DC bus)	10–100 µF electrolytic
1–100 kHz (power rail)	1–10 µF ceramic + bulk
1–50 MHz (IC supply pins)	100 nF X7R at each pin
> 50 MHz (high-speed)	10–100 pF + 100 nF combo

Use low-ESR X7R/C0G ceramics near the load; bulk capacitance further away. Too much ceramic without damping can resonate.

📊 Schematic Diagrams

Simplified topologies to visualize current paths and component roles. Green arrows mark the main conduction path; yellow marks the flywheel/discharge path.

Buck (step-down) — Q chops Vin; when on, energy flows through L into C and the load while D is reverse-biased. When Q opens, L keeps the current flowing and D freewheels. Output = D·Vin (CCM).

Boost (step-up) — Q on charges L while D blocks. Q off forces L's current through D into C and the load, summing L's voltage with Vin: output ≈ Vin/(1−D).

LDO linear regulator — An error amplifier drives a series pass device so that the feedback divider equals Vref; the difference (Vin−Vout) is dropped across the pass element as heat, so η ≈ Vout/Vin.

LC output filter — L in series blocks fast ripple while C shunts it to ground, leaving smooth DC across the load. Above fc the filter attenuates at 40 dB/decade.

Buck-boost (inverting) — One inductor but the output polarity is inverted: the diode freewheels L's current into a rail below common. Handy for split or negative supplies from a single positive input.

Flyback (isolated) — Energy is stored in the transformer core while Q is on, then released to the secondary — so voltage and output are isolated across the barrier. The turns ratio and duty set Vout, with no output-side inductor.

Inrush / soft-start — A cold NTC starts at high resistance to slow the bulk-cap charge into the load, then self-heats and drops. Watch steady-state loss and cooling time before hot re-plug.

SEPIC power stage — L1 and L2 (often a coupled pair) plus a series coupling capacitor Cs. The output is non-inverting and regulated above or below Vin; duty D = Vout/(Vin+Vout) in CCM. Choose Q and Cs rated for ≈ Vin+Vout.

Switching-loss overlap — While Vds falls (turn-on) and Id still rises, voltage and current overlap, dissipating Psw = ½·Vin·I·fsw·(tr+tf) at each edge. Shorter edges and lower fsw cut the shaded energy.

Ćuk inverting stage — L1, a series coupling cap Cs and L2, with the diode returning to the common rail so the output is the negative of the input. Energy is transferred mostly through Cs to a clean, non-rippled input and output current.

Buck ripple current & ΔV — The triangular inductor ripple ΔI flows into the output cap. The capacitance charges to a small parabola (ΔVc) while the ESR adds a near-rectangular step (ΔVesr); on electrolytic caps the ESR term usually dominates.

RC snubber — Place the series Rs·Cs from the switch drain to ground. When Q turns off, Ls drives the node and rings with the parasitic capacitance; the snubber absorbs that spike energy and critically damps it. Keep Cs small to limit the ½·C·V²·fsw loss.

Buck current ripple — While on, the inductor voltage is Vin−Vout and the current ramps up; while off it falls. The peak-to-peak ripple ΔI = (Vin−Vout)·D/(fsw·L) sets both the output ripple and the current the switch must carry.

Inrush charge — At switch-on the empty capacitor looks like a short: initial current jumps to Vin/R then decays as it charges. This stresses the rectifier, fuse and capacitor — use soft-start to round the peak.