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Timer, baud-rate, ADC, clock-tree and throughput calculators for firmware bring-up, plus condensed tables for common MCU families, clock sources, GPIO and power modes.

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Register dividers, BRR fields and prescalers are integer values — rounding changes timing. Always confirm clock-source frequencies and allowed divider ranges in the reference manual for your exact MCU.

Timer PWM & Overflow

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fPWM = Fclk / ((PSC+1) · (ARR+1)); PWM resolution = log2(ARR+1) bits. Add a compare value CCR to read the duty cycle.

Timer clock Fclk

Prescaler PSC

cnt

Auto-reload ARR

cnt

Compare CCR

cnt

PWM frequency

—

Period T

—

PWM resolution

—

Duty (CCR/ARR)

—

(PSC+1) and (ARR+1) are the actual counter values. Higher resolution means a longer period at the same clock.

UART Baud Rate & Error

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BRR = round(Fclk / (baud · oversampling)); actual baud = Fclk / (oversampling · BRR). Errors under ~2 % are usually usable for 8N1.

Peripheral clock Fclk

Target baud rate

Oversampling

Recommended BRR

—

Actual baud

—

Baud error

—

High oversampling (16×) gives finer BRR steps. If your clock cannot hit a clean divisor, pick a baud the exact part supports or add a direct/independent BRR mode.

ADC Resolution & Conversion

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V = code · Vref / 2^N; LSB = Vref / 2^N. Enter a code to read voltage or a voltage to read the code.

Resolution N

bit

Reference Vref

ADC code

cnt

Voltage V

LSB step

—

Full-scale code

—

Voltage at code

—

Code at voltage

—

Real ADCs add gain/offset error and noise; the quantization LSB is only the ideal step. Check INL/DNL and Vref accuracy in the datasheet.

PLL System Clock

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VCO = HSE / M × N; SYSCLK = VCO / P. M divides the source, N multiplies into the VCO, P scales it down to the core clock.

Oscillator HSE

Divider M

Multiplier N

Post-divider P

PLL VCO output

—

System clock SYSCLK

—

Keep the VCO inside the allowed range (often 100–432 MHz) and M/N/P within the exact part's limits. The value is valid only if the FLASH wait-states and APB prescalers fit the resulting SYSCLK.

Independent Watchdog Timeout

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T = prescaler · reload / LSI. The reload register is 0–4095; the prescaler divides the low-speed clock before the counter.

Low-speed clock LSI

Prescaler divider

Reload value

cnt

Watchdog timeout

—

Max timeout (reload 4095)

—

Feed the dog before the count hits zero or the MCU resets. LSI accuracy is coarse (±10–30 %), so leave margin: refresh at most a fraction of the computed timeout.

SPI Data Throughput

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Max bytes/s = SCLK / bits-per-frame · frame-bytes. Transfer time for a block = 8 · bytes / SCLK (8-bit frames).

SCLK frequency

Bits per frame

bit

Block size

Max bytes/second

—

Block transfer time

—

Real SPI rates are limited by the peripheral max, GPIO speed and PCB routing. This is the wire-level figure — software/DMA overhead adds time on top.

I2C Bit-Rate & Frame Time

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SCL = fclk ÷ (2·CCR) for the classic peripheral; bit time = 1/SCL. A frame = 1 start + 7 address + R/W + ack + N bytes (8+ack each).

Peripheral clock fclk

Divider CCR value

Target bit-rate

Bytes per frame (data)

Actual SCL frequency

—

Error vs target

—

Bit time

—

Frame time (addr+data)

—

This is the wire-level timing for a classic 7-bit controller. It excludes bus turnaround, repeated starts, multi-byte spanning and clock stretching by slow slaves; the I2C spec caps the divisor patterns per mode, so check the part's CCR bit layout.

Sleep Timer & Battery Life

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Wake-up period = reload ÷ LSE; average current = I·duty% + I(sleep)·(1−duty%); battery life = mAh ÷ avg current.

Wake clock f (e.g. LSE)

Counter reload value

Active current

Sleep current

µA

Active time duty

Battery capacity

mAh

Wake-up period

—

Average current

—

Battery life

—

Battery life assumes the full average current flows to the end of life — real cells self-discharge and lose capacity with temperature and cycles. Add derating and measure the sleep current; the LSE wake timer only stops power draw, not the regulator's own consumption.

📊 MCU Diagrams

Simplified views of a minimal MCU system, timer PWM timing, the PLL clock tree and GPIO output stages.

Minimal MCU system — A working MCU needs a decoupled supply, a reset that is pulled high, a clock source (crystal or RC) and access to the debug port (SWD) plus a boot-mode pin.

PWM counter & output — The timer counts from 0 to ARR; the output goes high until the counter reaches CCR. Adjusting CCR changes only the duty, while ARR sets both the period and the resolution.

PLL clock tree — The oscillator is divided by M, the PLL multiplies by N to a VCO, and the post-divider P scales it to SYSCLK, which feeds the AHB/APB domains and peripherals.

GPIO output stages — Push-pull drives the pin high and low through two transistors; open-drain only pulls low and needs an external pull-up, which lets the line rise to whatever rail it is tied to.

I2C address frame — SCL clocks SDA through a START condition then 7 address bits plus the read/write bit; the addressed slave stretches the clock if it needs more time and acks by pulling SDA low on the next clock.

Power-mode state machine — The core advances Running → Sleep → Stop → Standby, trading wake latency against draw. Sleep wakes on any interrupt, Stop on EXTI/RTC, Standby only on reset or a wake-up pin — and loses RAM contents.

Interrupt servicing — When an event asserts an IRQ, the core finishes the current instruction, saves context and jumps to the ISR after a fixed latency, then returns to the main loop. Keep ISRs short so lower-priority work still meets its deadline.

📚 MCU Reference Tables

Condensed specs for common MCU families, clock sources, GPIO electricals and power modes. Values are typical — always refer to the part's datasheet.

Common MCU Families

Part	Core	Flash/RAM	Max clock	Peripherals	Notes
STM32F103C8	Cortex-M3	64K/20K	72 MHz	3×TIM, USART×3, SPI, I2C, ADC	Blue Pill classic; USB, cheap
STM32G030	Cortex-M0+	32K/8K	64 MHz	TIM×6, USART×2, ADC, DAC	Low-cost HSI-only, 32-bit
ATmega328P	AVR	32K/2K	20 MHz	3×TIM, UART, SPI, I2C, ADC	Arduino Uno; 5 V native
PIC16F877A	8-bit PIC	14K/368	20 MHz	3×TIM, USART, MSSP, ADC	Legacy but everywhere; 40-pin
MSP430G2553	16-bit RISC	16K/0.5K	16 MHz	TIM, UART, SPI, I2C, ADC	Ultra-low power, analog
nRF52840	Cortex-M4F	1M/256K	64 MHz	BLE, USB, QSPI, NFC, ADC	Radio + lots of RAM
ESP32	Xtensa LX6	4M/520K	240 MHz	Wi-Fi, BT, UART×3, SPI, ADC	Wireless SoC; external flash
RP2040	Cortex-M0+ ×2	2M/264K	133 MHz	PIO, DMA, USB, ADC, I2C/SPI	Pico; programmable IO

Clock Sources

Source	Typical freq	Accuracy	Notes
HSI (internal RC)	8 / 16 MHz	±1–3 %	Boots instantly; drift with temperature
HSE (external)	4–25 MHz	±20–100 ppm	Crystal; the source for accurate timing / USB
LSI (internal)	32 / 40 kHz	±10–30 %	Drives IWDG / low-power auto-wake; coarse
LSE (external 32k)	32.768 kHz	±20 ppm	Watch crystal; keeps RTC accurate in sleep

GPIO Electricals (typical)

Parameter	Typical value	Notes
Input high VIH	0.6–0.7 × VDD	Above this reads as logic 1
Input low VIL	0.3–0.4 × VDD	Below this reads as logic 0
Output push current	4–20 mA	Do not drive LEDs/relays directly
Pull-up / pull-down	20–50 kΩ	Weak; not for strong loads
Max toggle rate	5–50 MHz	Needs matching output speed config
Absolute max V / VDD	VDD ± 0.3–0.5 V	Over-driving pins damages the IO

Low-Power Modes

Mode	Wake sources	Typical draw	Notes
Sleep	Any interrupt	μA–mA	CPU halts, clock keeps running
Stop	EXTI, RTC, wake-up pin	µ–few µA	Peripherals off, SRAM retained
Standby	Reset, wake-up pin, RTC	µA and below	Everything off; RAM lost