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EMC & Signal Integrity

Rise-time bandwidth, critical trace length, crosstalk and decoupling resonance calculators, plus reference tables for signal speeds, trace limits and cap resonance.

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Bandwidth–rise-time, crosstalk and resonance values are estimates that depend on your exact stack-up, geometry and components. Confirm against the PCB manufacturer, the driver datasheet and, where possible, simulation or a scope measurement.

Rise Time ⇄ Bandwidth

BW = 0.35 / tr (10–90%). A fast edge needs a wide measurement/signal bandwidth: 0.35 ns rise ≈ 1 GHz. Enter one to get the other.
ns
GHz
Bandwidth f3dB
—
Equivalent rise time
—
The 0.35 factor assumes a first-order (RC) edge. Many scope and logic specs use 10–90%; 20–80% edges use ≈0.22. When cascading stages, add bandwidths in quadrature: 1/BW² = Σ 1/BWᵢ².

Critical Trace Length

A trace acts as a transmission line when its propagation delay approaches the rise time — roughly l_crit = tr · v / 6 (so the round-trip stays < tr). Above this, control impedance and terminate.
ns
—
Velocity v
—
λ/10 at BW
—
Critical length
—
FR-4 (εr ≈ 4.2–4.6) propagates at about 125–150 mm/ns. Below the dash-line "rule of 6" (delay ≤ tr/6) a trace is electrically short and lumped; beyond it treat it as a transmission line with a controlled Z and a series/parallel termination.

Crosstalk Estimate

Capacitive noise Vₘ = R · Cₘ · dV/dt and inductive noise Vₗ = Lₘ · dI/dt. Fast edges over coupled length inject current into a quiet victim via mutual capacitance Cₘ and mutual inductance Lₘ.
Ω
F
V/s
A/s
H
Capacitive Vₘ
—
Inductive Vₗ
—
Total noise
—
Crosstalk grows with parallel (coupled) length and edge speed. Reduce it with wider spacing, a ground guard trace between the lines, or by routing aggressor and victim on different layers over a solid ground plane.

Decoupling Cap Resonance

A real capacitor resonates at f0 = 1 / (2π·√(ESL·C)). Below f0 it behaves capacitively, above f0 inductively; the SRF is where the bypass is lowest-impedance and most effective.
F
H
Resonance f0
—
Z at f0
—
Assumed ESR
—
ESL and ESR come from the capacitor's datasheet; the parallel mounting inductance of vias and pads adds significantly. Mixing values (e.g. 100 nF + 10 nF + 1 nF) blankets more of the spectrum, but avoid two caps resonating at nearly the same frequency (anti-resonance peak).

Reflection & Termination

A mismatch reflects part of an incident wave: Γ = (ZL − Z0)/(ZL + Z0). VSWR = (1+|Γ|)/(1−|Γ|), return loss = −20·log10|Γ|. A source-termination resistor Rs = Z0 − Zout absorbs it at the driver.
Ω
Ω
Ω
Reflection Γ
—
VSWR
—
Return loss
—
Source term Rs
—
Γ → 0 (VSWR → 1) when the load equals Z0. A short (ZL=0) gives Γ=−1, an open (ZL=∞) gives Γ=+1 — both fully reflect. For point-to-point lines a source or load end-termination works; for buses use end (parallel) termination and keep stubs short. Ideal estimates — real connectors and vias add parasitics.

Via Inductance (SI)

A through-hole via behaves inductively at high frequencies: L ≈ 5.08·h·[ln(4h/d)+1] nH (h, d in inches). At jωL this series impedance degrades return paths and adds signal-bounce on fast edges.
mm
mm
Via inductance
—
Reactance at 1 GHz
—
The inductance is proportional to via height, so a shorter via means less discontinuity — on thick boards use thin (blind) vias or move to a thinner stack for critical high-speed nets. Parallel vias divide the effective inductance. This is a rough estimate; field solvers give the true value including return path.

Ground-Loop Induced Voltage

A changing magnetic field links the area between signal and return paths: V = 2πf·B·A is induced around the loop.
Hz
µT
cm²
Induced emf
—
The induced emf is proportional to loop area, so minimise the separation between signal and return (tight plane or twisted pair). At high frequency a star ground creates several large loops — prefer a solid return plane.

Shielding Effectiveness

SE = A(absorption) + R(reflection). For a solid metal plane and far-field source: A ≈ 3.34·t_mil·√(f·μr·σr), R ≈ 168 − 10·log10(f·μr/σr).
MHz
mm
—
—
Absorption A
—
Reflection R
—
Total SE
—
Absorption grows with √f and thickness (about 6 dB per skin depth); reflection falls at high frequency. Thin, conductive, seam- and hole-free shields work best at high f; at low f you need magnetic material (high μr) or thicker walls.

📊 Signal & Coupling Diagrams

An edge with rise time, the transmission-line threshold, parallel-trace coupling and a capacitor's impedance curve.

EDGE + RISE TIME (10–90%) 1.0 0.9 0.1 0 tr = 10%→90% BW ≈ 0.35/tr

Rise time & bandwidth — The 10–90% rise time of a logic edge sets the bandwidth the interconnect and the measuring scope must support. Faster edges couple into more places and need careful routing.

ELECTRICALLY SHORT vs LONG driver R l_crit = tr·v/6 delay < tr/6 transmission line driv 1 Z0, termination needed

Critical length — Below the threshold the line is lumped and a simple RC model suffices. Once the round-trip delay approaches the rise time you must control impedance and add near or far-end termination.

PARALLEL-TRACE COUPLING AGGRESSOR VICTIM Cm, Lm noise injects into victim quiet net

Coupling — Mutual capacitance Cₘ injects displacement current, mutual inductance Lₘ couples flux, so a fast edge on the aggressor induces noise on the quiet victim. Spacing, a guard trace and a solid plane reduce it.

|Z| vs FREQUENCY (SRF) f |Z| capacitive → ← inductive f0 = 1/(2π√(ESL·C)) min |Z|

Capacitor resonance — Impedance falls with C until ESL takes over and pushes it back up. Use each cap near its SRF; combine values so the peaks and valleys of several caps overlap, keeping impedance low across the frequency band of interest.

MISMATCH & REFLECTION driver Rs Z0 line ZL Σ reflected wave if ZL ≠ Z0 series Rs = Z0 − Zout kills the round-trip bounce

Reflection & termination — An incident edge hits a load that differs from Z0 and reflects back, ringing the line. Making Rs equal Z0 − Zout (source termination) or ZL = Z0 (parallel end termination) absorbs it and removes the ringing.

VIA = INDUCTIVE DISCONTINUITY L_via series L top trace bottom trace fast edge ringing shorter via → less L → use parallel vias for critical nets

Via inductance — Every layer change adds a via whose inductance appears in series with the signal. On fast edges it acts like a small choke, adding delay, ringing and a degraded return path. Reduce it with short, thick and parallel vias.

GROUND LOOP signal path loop area A (return path) B → V = 2πf·B·A Φ = B·A

Ground loop — Any separation between the signal path and its return encloses an area. A magnetic field through it injects an emf proportional to that area — shrink the loop and keep return current close beneath the signal.

SHIELDING (SE = A + R) shield incident reflected R absorbed A SE = A + R few dB remaining absorption ⇑ √f · thickness; reflection ⇓ at high f

Shielding — A conductive shell reflects part of an incident wave and absorbs the rest as it penetrates. Absorption dominates at high frequency; reflection carries the low-frequency end, so the shield must have continuous conductivity and tight seams.

📚 EMC / SI Reference Tables

Signal speeds, critical-length rules and decoupling values. Figures are representative — validate against the specific standard, driver and stack-up.

Rise Time ↔ Bandwidth Examples

Signal / standardTypical tr≈ bandwidth
I2C / UART~100 ns–1 µs0.35–3.5 MHz
SPI / 100 MHz~3 ns~110 MHz
USB 2.0~0.3 ns~1.2 GHz
Gigabit Ethernet~150 ps~2.4 GHz
PCIe Gen3 (8 G)~40 ps~8 GHz

Trace Length & Termination Rules

Rule of thumbRuleNote
λ/10 (lumped)l < 0.1·λbelow this a trace is lumped
Rule of 6delay ≤ tr/6largest length that can be treated as electrically short
Speed of FR-4~150 mm/ns≈ 60% of speed of light
When to terminate2·tpd > trround trip approaches rise time

Decoupling Value & SRF

CapacitorX7R / C0G ESR≈ SRF (0402)Use
1 µF~5–10 mΩ~10 MHzbulk, rail stabilization
100 nF~10–50 mΩ~100 MHzIC VDD decoupling
10 nFhigher~300 MHzhigh-frequency bypass
1 nFhighest~1 GHzRF / fast-edge planes