Protocols & Communication

🔤 UART

Asynchronous serial over two wires (TX/RX). Common logic-level standard (TTL/3.3 V).

Common levels

3.3 V logic	High ≥ 2.0 V, Low ≤ 0.8 V (typ)
5 V TTL	High ≥ 2.4 V, Low ≤ 0.5 V (typ)
RS-232	≥ +3 V = 0, ≤ −3 V = 1; up to ±13 V

Standard baud rates

300 · 1200 · 2400 · 4800 · 9600 · 19200 · 38400 · 57600 · 115200 · 230400

Idle / frame

IDLE(High) | start(0) 8 data bits (LSB first) [parity] stop(1[,2])

Idle high; start bit (low), 8 data bits (LSB first), optional parity, 1 or 2 stop bits.

See the Protocol Timing Calculators above to convert baud rate to bit and byte times.

🔀 I2C

Two-wire (SCL, SDA), open-drain with pull-ups, multi-master, 7-bit (or 10-bit) addressing.

Voltage

VDC rail dependent; logic high pulled to VDD, low ≈ 0 V

Standard speeds

Standard 100 kbit/s · Fast 400 kbit/s · Fast-mode+ 1 Mbit/s · High-speed 3.4 Mbit/s

Pull-up resistor

Typically 1.8–10 kΩ depending on bus speed and capacitance; e.g. 4.7 kΩ @100kHz, 1–2 kΩ @400kHz. Range limited: SCL/SDA low voltage VIH>0.7×VDD, VIL<0.3×VDD.

Addressing

7-bit address is written twice on the bus (addr << 1 | R/W); common addresses: 0x68 (MPU6050), 0x76 (BMP280), 0x50 (24C02 EEPROM).

🌐 SPI

Serial Peripheral Interface: full-duplex, 4 wires (SCLK, MOSI, MISO, SS). Master controls clock.

Signals

SCLK · MOSI (master→slave) · MISO (slave→master) · SS/CS (active low)

Max speed is set by the slave datasheet and board wiring; typical 1–50 Mbit/s.

Modes (CPOL, CPHA)

Mode 0	(0,0) clock idle low, data on rising edge — by far the most common
Mode 1	(0,1) clock idle low, data on falling edge
Mode 2	(1,0) clock idle high, data on falling edge
Mode 3	(1,1) clock idle high, data on rising edge

🔗 USB

Universal Serial Bus — speed classes and typical connector/config pins.

Speed classes

USB 1.1 Full-Speed: 12 Mbit/s
USB 2.0 Hi-Speed: 480 Mbit/s
USB 3.x SuperSpeed: 5 / 10 / 20 Gbit/s

VBUS voltage

5.0 V (±5%); maximum negotiated current per type (default 100 mA, up to 500 mA / 900 mA / 5 A on USB-PD)

Data pins (Type-A/C)

Type-A: 1=VBUS 2=D− 3=D+ 4=GND
Type-C: D+/D− on CC-defined orientation (A6/B6)/(A7/B7)

Type-A: 1=VBUS 2=D− 3=D+ 4=GND · Type-C: D+/D− on pins (A6/B6)/(A7/B7) in CC-defined orientation

🔁 RS-485 (EIA-485)

Differential, multipoint bus for industrial communications; balanced A/B pair.

Differential levels

Idle A > B (logical 1); driven A < B (logical 0). Range ≈ −7 V to +12 V common-mode.

Termination

120 Ω termination at each cable end for long runs; stub lengths kept short.

Speed vs. length

Coarse rule: 100 m @ 9.6 kbit/s down to ~10 m @ 10 Mbit/s (cable-dependent).

🌍 Ethernet (Twisted Pair)

Auto-negotiated speeds over twisted-pair; pairs are twisted and use differential signaling.

Common speeds

10BASE-T: 10 Mbit/s (2 pairs)
100BASE-TX: 100 Mbit/s (2 pairs)
1000BASE-T: 1 Gbit/s (4 pairs)

1000BASE-T pin mapping

1/2 = Pair B · 3/6 = Pair A
4/5 = Pair C · 7/8 = Pair D

Magnetics

RJ45 usually integrates a magnetics transformer (isolation + common-mode) — plan it into the footprint.

🔢 Common I2C Device Addresses

Common 7-bit addresses (bottom; A0–A2 pins often shift them). Always confirm with the datasheet.

Device	7-bit addr	Notes
MPU6050 IMU	0x68	AD0 = 1 → 0x69
BMP280 / BME280	0x76	or 0x77 (SDO pin)
AT24C02 / 24LC256 EEPROM	0x50	+ A0–A2 address pins (0x50–0x57)
ADS1115 16-bit ADC	0x48	+ ADDR pin select (0x48–0x4B)
DS1307 RTC	0x68	shared by many RTCs
PCA9685 PWM driver	0x40	+ A0–A5 (0x40–0x7F)
HTU21D humidity	0x40	also 0x40-based sensors

🚗 CAN (CAN 2.0 / CAN FD)

Differential two-wire bus (CANH/CANL) for robust automotive and industrial links.

Levels

Dominant drives CANH≈3.5 V / CANL≈1.5 V; recessive ≈2.5 V each. Differential: dominant ≈2 V, recessive ≈0 V. Common-mode −2 V…+7 V.

Typical bitrates

Classic: 125 k · 250 k · 500 k · 1 Mbit/s. CAN FD adds a high-speed data phase up to ~5–8 Mbit/s.

Termination

120 Ω at each bus end to avoid reflections; keep stubs short.

Addressing

No device address — each message carries an identifier; receivers filter by ID/acceptance mask.

Keep total cable < ~40 m (typ) for 1 Mbit/s; use twisted/shielded pair and ground the shield at one end.

🧵 1-Wire

Single data line + ground, open-drain with pull-up; every device carries a unique 64-bit ROM address.

Pull-up

~4.7 kΩ pull-up to VDD; strong pull-up helps parasite-power/time-critical ops.

Speeds

Standard ~15.4 kbit/s; overdrive up to ~142 kbit/s.

Addressing

Host reads each device's 64-bit ROM code, then addresses it individually on the single wire.

Only one driver active at a time; parasite power can supply low-power slaves from the data line.

🚌 LIN (LIN 2.x)

Low-cost single-wire automotive sub-bus (12 V). One master, up to 15 other nodes.

Bus

Single wire at Vbat (12 V nominal); recessive ≈ Vbat, dominant ≈ 0 V.

Bitrate

Typical 9.6 / 19.2 kbit/s (up to 20 kbit/s); the master drives the schedule.

Addressing

6-bit frame identifier (0x00–0x3F); communication is role-based on a schedule table (who sends/receives).

⏱️ Protocol Timing Calculators

Convert baud/clock rates to time and throughput for the most common serial interfaces. Results are estimates — confirm against the peripheral datasheet and nominal clock tolerance.

UART Timing

Include in PDF

Bit time = 1 / baud. With an 8-N-1 frame (start + 8 data + stop) each byte costs 10 bit-times, so the usable payload rate is 8/10 of the baud rate.

Baud rate

b/s

Bit time

—

Byte time (8-N-1)

—

Payload rate

—

Real throughput depends on flow control, framing overhead and clock error between the two UARTs (allowed ± a few %). On an MCU, baud is often generated from a PLL/peripheral clock that may not divide exactly — check the actual error in software.

I2C Transaction Time

Include in PDF

For a 7-bit write of N payload bytes: bits = 11 + 9·N (start, 7-bit address, R/W, ACKs, data, stop). Time = bits / fSCL.

Clock frequency fSCL

Hz

Data payload

bytes

Frame bits

—

Transaction time

—

Throughput

—

The slave can stretch SCL or add repeated-start and register-address bytes, which lengthens real transactions. Reads often do an extra address+restart. This is the ideal no-stretch case for a 7-bit write.

SPI Transfer Time

Include in PDF

Transfer time = bits / SCLK. Full-duplex shifts a byte in and out on the same clock edge, so time is set purely by the clock and the transfer length.

SCLK frequency

Hz

Transfer length

bits

Transfer time

—

Data rate

—

Max byte rate

—

The practical clock is limited by the slave's maximum SCLK and by bus wiring (each slave may need a lower clock). In practice chip-select assertion, setup/hold margins and interrupt round trips add overhead well beyond the raw shift time.

CAN Bit Timing

Include in PDF

Each bit is a set of time quanta (TQ). Bit rate = fOSC / (prescaler · TQ_total). Sample point = (Sync + Prop+PS1) / TQ_total — place it late (~80–87%) for robustness.

Oscillator fOSC

Hz

Prescaler

Sync seg

TQ

Prop + phase1

TQ

Phase seg2

TQ

TQ duration

—

Bit rate

—

Sample point

—

Keep phase2 ≥ SJW at the chosen sample point; the propagation+phase1 segment must cover the bus round-trip time and driver/receiver delays (the length of the network). On classic CAN only 8 data bytes fit; CAN FD uses a faster data phase.

🖼️ Protocol Diagrams

Simplified waveforms and bus topologies for the common serial protocols on this page.

UART — UART frame on TX: idle high; the start bit pulls low, 8 data bits follow LSB-first, optional parity, then 1–2 stop bits high.

I2C — I2C: START (SDA falls while SCL high) then ADDRESS+R/W byte and ACK. Open-drain lines pulled up — no driver fights.

I2C start / data / stop timing — Data bits are stable while SCL is high and may change only when SCL is low. A START is SDA falling while SCL is high; a STOP is SDA rising while SCL is high.

SPI — SPI: the master drives SCLK, MOSI and chip-select nSS; the slave returns MISO. Full-duplex, no addressing.

RS-485 (EIA-485) — RS-485: differential A/B line with a 120 Ω termination at both ends. Idle state A > B (logic 1).

CAN (CAN 2.0 / CAN FD) — CAN: dominant drives CANH up to ≈3.5 V and CANL down to ≈1.5 V (differential ≈2 V); recessive ≈2.5 V on each wire.

Interrupt Vector — Vector table: the lowest address holds the highest-priority entry. Reset, NMI and faults come first, then each device IRQ maps to an entry at offset 4×N (ARM Cortex-M).

NVIC Priority Grouping — NVIC priority bits split into preemption and sub-priority fields (AIRCR.PRIGROUP). Numerically lower value = higher priority; a higher preemption level can preempt execution. Mapping is device-specific — see your MCU reference manual.

STM32 IRQ Distribution — NVIC IRQ numbers for common STM32F1 peripherals: IRQn = vector index − 16 (IRQ0 is the first external interrupt). The mapping is device-specific — confirm against the part's IRQn header.

SDIO / SD — SDIO host drives CLK and issues commands on CMD; the card returns responses on CMD and transfers data on DAT0–3 (4-bit mode). CMD/DAT need pull-ups; signaling is 3.3 V or 1.8 V.

SDIO Command Token — SD command/response frame: start(0), transmission bit, 6-bit index, 32-bit argument/status, CRC7 and end(1) = 48 bits. Host command transmission bit 1; card response bit 0.

USB differential — D+ and D− carry the data as a differential pair (≈90 Ω); the D+ pull-up on the device tells the host the speed class (full-speed here). Shield guards EMI over the cable.

Ethernet MDI — Magnetic isolation transformer sits between the PHY pins and the RJ45 jack; its center taps return to chassis ground. The twisted pair is a 100 Ω differential line with common-mode rejection.