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Digital Logic

Pull-up sizing, RC edge times, CMOS power and logic fanout calculators, plus logic-family, pull-up and gate-symbol reference tables with wiring diagrams.

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Logic thresholds, drive currents and edge rates are family-dependent — confirm exact values in the datasheet of the part and of every device on the bus before sizing pull-ups or fanout.

Open-Drain Pull-Up

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Rp,min = (VDD − VOL)/IOL limits the sink current; Rp,max = tr / (CL · ln((VDD−VIH)/VDD)) keeps the rise fast enough. Choose R between the two.

Supply VDD

Low level VOL

Sink current IOL

Rise time tr

Load cap CL

Rp min (sink)

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Rp max (rise)

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VIH and bus capacitance together set the upper bound. Add a little margin and prefer a standard E24 value between the two limits.

RC Rise Time & Bandwidth

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tr = 2.2 · R · C (10–90 %); time constant τ = R · C; cutoff f = 1/(2πRC). A larger R or C slows the edge and lowers the corner.

Resistance R

Capacitance C

Rise time tr

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Time constant τ

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Cutoff f3dB

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At the −3 dB cutoff the response is already −45°/dec down. For a clean digital edge keep f3dB well above the data rate.

CMOS Dynamic Power

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P = C · V² · f. Switching a capacitance C at supply V and frequency f dissipates P; higher DVFS voltage dominates because it enters squared.

Load capacitance C

Supply voltage V

Frequency f

Dynamic power P

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Static/leakage and short-circuit power add on top. Per-gate power scales linearly with toggling activity, so gating clocks saves real power.

Logic Fanout

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Fanout = min(IOH/IIH, IOL/IIL). How many inputs one output can drive, limited by the weaker of the source/sink capability versus each input's load.

Output high IOH

Output low IOL

Input high IIH

Input low IIL

Maximum fanout

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Edge rate is the real limit for high-speed CMOS; even if the DC fanout allows more loads, the added capacitance may slow the edges too much. Account for trace and input capacitance too.

📊 Logic Diagrams

Open-drain bus pull-up, a CMOS inverter pair, a NAND gate with its truth table and a clocked D flip-flop.

Open-drain bus — Every node can only pull the shared line low; when all transistors are off the pull-up Rp restores it to VDD. This wired-AND bus works for I2C, 1-Wire and reset lines.

CMOS inverter — The PMOS pulls the output to VDD when Vin is low; the NMOS pulls it to GND when Vin is high. Only one transistor conducts at a time, so steady-state current is near zero.

NAND gate — Output is low only when every input is high, and high otherwise. Universal in a sense: with a NAND you can build any other gate, which is why flash memories are made of them.

D flip-flop — On every rising clock edge the output Q copies D and holds it until the next edge. Setup/hold times around the edge must be met: the input must be stable before tsu and held after th.

Tri-state bus — Each driver can drive high, low or release (High-Z). Only one cell drives at a time; the others float so their outputs share a single wire without contention.

Push-pull vs open-drain — A push-pull output actively drives both rails; an open-drain can only sink low and must be pulled up — ideal for a shared bus or for level-shifting to a higher rail.

📚 Logic Reference Tables

Family electricals, pull-up/termination guidance and common gate functions. Values are typical at VDD = 5 V or 3.3 V — confirm with each datasheet.

Logic Families (typical)

Family	VCC	VIH	VIL	tpd	IO	CMOS out
74LS / TTL	5 V	2.0 V	0.8 V	≈10 ns	±0.4 mA	needs pull-up
74HC	2–6 V	0.7·VCC	0.3·VCC	7–20 ns	±4 mA	full rail CMOS
74HCT	4.5–5.5 V	2.0 V	0.8 V	8–20 ns	±4 mA	TTL input, CMOS out
74LVC	1.65–3.6 V	0.6·VCC	0.3·VCC	2–4 ns	±16–24 mA	fast, 3.3 V
74AHC	2–5.5 V	0.65·VCC	0.35·VCC	3–8 ns	±8 mA	fast, drive
CD40xx	3–15 V	0.7·VDD	0.3·VDD	30–120 ns	±1–6 mA	slow, high swing

Pull-up & Termination

Item	Common value	Use
I2C pull-up	1–4.7 kΩ	bus capacitance trades with speed
SPI / GPIO pull-up	10 kΩ	idle state, default weak
Reset pull-up	10 kΩ	keep MCU out of reset
LED resistor	330–1 kΩ	limit diode current
Series termination	22–50 Ω	match Z0, damp ringing

Common Gate Functions

Symbol	Output rule	Typical use
AND	Y = A·B	gating / enable, all-high conditions
OR	Y = A+B	any-one triggers, combiner
NAND	Y = A·B	universal gate, memory cells
NOR	Y = A+B	universal gate, active-low logic
XOR	Y = A⊕B	parity, comparator, adder