Memory & Storage Interfaces

Memory hierarchy — Fast, small, expensive memory sits close to the CPU; large cheap storage sits far away. Caches copy frequently used data upward so most accesses hit the fastest level.

SPI / QSPI NOR — A small pin count boots code from NOR flash: CLK and chip-select plus bidirectional IO lines. QSPI uses four IO lines to fetch data up to four bits per clock for fast xip (execute-in-place).

I2C EEPROM — SDA and SCL are open-drain with pull-ups to VDD; the controller addresses each EEPROM by its strap pins. A3=1 on larger parts extends the page address beyond the three pins shown.

6-T SRAM cell — Two cross-coupled inverters hold a bit; two pass transistors gate it onto the bit lines when the word line is high. Static — no refresh, but needs a constant supply and six transistors per bit.

1-T DRAM cell — A single access transistor and a small capacitor store the bit; the charge leaks away, so every row must be refreshed. Far denser and cheaper per bit than SRAM, which is why RAM is DRAM.

Parallel memory bus — Wide address and data buses plus chip-select, write and read strobes talk to the array directly. Fast and simple, but each bit costs a pin — why high-density parts moved to SPI/QSPI/OSPI.

SD / SDIO card interface — A clock plus a bidirectional command line and 4 data lines talk to one card. Closing the RD/WR CRC in firmware and handling busy (DAT0 low) correctly matters more than raw speed.

DDR SDRAM interface — Address and bank pins plus bidirectional data and a strobe pin per byte lane. The data strobe is source-synchronous, so timing is captured against DQS rather than the CPU clock; short matched traces and a controlled impedance matter.

NAND block & page layout — A block holds many pages; a page is typically a few KiB of data plus a spare (OOB) area. Erase happens per-block, program per-page, and bad blocks are marked in the OOB — wear leveling and ECC live in the controller.

Address decode & chip select — Upper address lines go to a decoder that raises exactly one chip-select per window while the lower lines and data bus are shared. Only the selected chip responds, so each region maps to a unique address range.