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PCB Design Rules

Practical design references: trace current, controlled impedance, via sizes, clearances and manufacturing capabilities.

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Figures marked "typical" vary by laminate, plating, temperature and fabricator. Always confirm with your manufacturer's capability sheet before ordering. IPC-2221/IPC-2152 formulas are approximations.

Trace Current Capacity

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I = k × A^0.725 × ΔT^0.44, external layer k=0.048, internal k=0.024 (A = cross-section in mil²).

Current (A)

Temp rise (C)

°C

Copper (oz)

Layer

Minimum trace width

—

Width (mil)

—

Area (mil²)

—

This is an estimate — reduce current for internal layers, high ambient temperature, long runs and thin copper.

Microstrip Impedance

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Approximate: Z0 ≈ (87/√(Er+1.41)) × ln(5.98h / (0.8w + t)) (Wheeler) — for demonstrative comparison only.

Dielectric h (mil)

mil

Width w (mil)

mil

Thickness t (mil)

mil

Impedance Z0

—

Real impedance depends on Er tolerance, etch, solder-mask and stackup. Use a field solver for production-controlled impedance.

🥉 Copper Weight Equivalents

1 oz/ft² is the standard unit for inner/outer copper.

Weight (oz/ft²)	Thickness (µm)	Thickness (mil)
0.5 oz	17.5 µm	0.7 mil
1 oz	35 µm	1.38 mil
2 oz	70 µm	2.76 mil

🏭 Standard Manufacturing Capabilities

Typical limits for standard 2-layer FR4 boards. These are mid-range values that most fabs meet — verify with your supplier; tighter capabilities often cost more.

Parameter	Typical standard	Advanced (cost+)
Min trace width/spacing	6 / 6 mil	3–4 / 3–4 mil
Min drill hole size	0.3 mm (12 mil)	0.2 mm (8 mil)
Min annular ring	6 mil	4 mil
Board thickness	1.6 mm	0.4 – 6 mm
Min copper weight	1 oz (35 µm)	0.5 oz
Finish (surface)	HASL	ENIG, OSP, Immersion Ag
Min finished hole	0.3 mm	0.1–0.2 mm

Differential Impedance (Microstrip)

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Rough equal-width estimate Zdd ≈ 2·Z0·(1 − 0.48·e^(−0.96·s/h)). Not for production.

Dielectric h

mil

Width w

mil

Edge spacing s

mil

Thickness t

mil

Differential Zdd

—

Approximation only — coupling, stackup, solder mask and manufacturing dominate. Validate prototypes by TDR.

Trace Resistance & Voltage Drop

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A straight trace is a resistor: R = ρ·L/A with copper ρ ≈ 1.72×10⁻⁸ Ω·m. A = width × thickness (1 oz ≈ 35 µm). Vdrop = I·R and Ploss = I²·R follow directly.

Trace length L

Trace width w

mil

Copper

Current I

Resistance R

—

Voltage drop

—

Power loss

—

Resistance is proportional to length and inversely to cross-section, so doubling the trace width halves R. Copper resistivity rises to ≈2× at 100 °C — add margin for hot, thin or internal traces, and check the real effective width after etching.

Via Resistance & Inductance

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A via's copper barrel is a thin tube: its resistance is set by the plated wall (≈25 µm typical), L_via ≈ 5.08·h·[ln(4h/d)+1] nH (h, d in inches). A fast edge sees the inductance long before the small resistance.

Drill diameter d

Via height h

Current I

Barrel resistance

—

Via voltage drop

—

Inductance

—

A single via's barrel resistance is usually a fraction of a milliohm, so current capacity is rarely the limit — but its ~0.5–1 nH inductance adds impedance jωL at high frequency and slows fast edges. Stitch parallel vias (value them in parallel) for power and high-speed return currents. Plating thickness varies by fabricator (≈20–30 µm); verify with your supplier.

🕳 Standard Through-Hole Via Sizes

Common drill sizes, suggested pad and typical use (fabricator defines exact values).

Typical use	Drill bit (mm)	Pad (mm)
Signal / low-current	0.3	0.6
General-purpose	0.4	0.7
Power / via-stitching	0.6	1.0
Component / THT	0.8	1.4

📚 Common Layer Stackups

Typical 2- and 4-layer FR4 choices.

Configuration	Stackup
2-layer · 1.6 mm	Top signal · 1.6 mm core · Bottom signal (refill planes where useful)
4-layer · 1.6 mm	Signal · GND · VCC (split) · Signal; 1 oz outer / 0.5 oz inner typical

🔥 Decoupling & Thermal Quick Rules

Rules of thumb — adapt to your power and thermal requirements.

Decoupling	Put 100 nF close to each IC VCC pin; add 10 µF bulk at board entry; use the smallest feasible package to cut ESL.
Ground / return	Keep a continuous ground plane under high-speed traces; do not split the plane beneath signal crossings.
Thermal vias	Use small arrays of 0.3–0.5 mm vias under/exposed pads to spread heat to planes.
Copper pour	Flood fills help current and heat; watch for narrow necks that overheat.

✅ Pre-Production Checklist

Sanity checks before sending Gerbers.

DRC runs clean (no unresolved violations)
Netlist matches schematic
Output data complete: Gerbers + drill file, correct layers and origin
Board outline and dimensions correct; vias and pads on grid
Fabrication/assembly notes updated (finish, stackup, special)
Bill of materials matches footprints, and polarized parts orient correctly

📐 Stackup & Layout Diagrams

Visualize the cross-section that sets impedance and the return-current path you must keep continuous across planes.

Microstrip cross-section — The trace sits on a dielectric of height h over a solid ground plane; impedance is set by w, h, er and copper thickness t. Keep the plane continuous under the trace to hold Z0 stable.

vias GND plane slot return detours around slot = big loop keep it local

Stitching & return path — A signal crossing a slot in the ground plane forces the return current around it, enlarging the loop. Stitching vias on both sides keep the return path short and the loop tiny.

Trace & via resistance — A long thin trace and each via add a series resistance (and the via an inductance) into a net. These drops matter for precision references and return paths — model them and keep high-current and high-speed nets short and wide.